ZHANG Yu-long, WEN Yu, ZHENG Guang-zhou. Failure Analysis of SOI CMOS Circuit After Steady-state Life Test[J]. Failure Analysis and Prevention, 2022, 17(3): 195-199, 208. DOI: 10.3969/j.issn.1673-6214.2022.03.010
    Citation: ZHANG Yu-long, WEN Yu, ZHENG Guang-zhou. Failure Analysis of SOI CMOS Circuit After Steady-state Life Test[J]. Failure Analysis and Prevention, 2022, 17(3): 195-199, 208. DOI: 10.3969/j.issn.1673-6214.2022.03.010

    Failure Analysis of SOI CMOS Circuit After Steady-state Life Test

    • The failure analysis of the input leakage of the SOI COMS circuit after steady-state life test was carried out. The possible failure causes such as breakdown caused by abnormal power off, ion contamination, abnormal internal atmosphere, external surface pollution of chip and Electro-Static discharge (ESD) were investigated and analyzed. The failure cause of the circuit was identified as that ESD protective equipment was not in good condition, which led to breakdown of the diode at the input port of circuits caused by ESD generated during the test. The failure mode was repeated and verified by ESD test equipment simulation and original test process simulation. In the test process of SOI CMOS circuit, even if the tester wears an antistatic wrist strap and finger-cots as required, it is also easy to cause ESD failure of samples while the working status of corresponding equipment is poor. The failure mode is usually microampere leakage at the input port of the circuit, which will be partially recovered after high temperature annealing. It is recommended to select metal antistatic wrist straps and special antistatic finger-cots during the test. If nylon wrist straps are selected, it must be replaced regularly.
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